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[Other] fpgaandveriloghdl

Description: FPGA中嵌中高级课件,非常有用的课件，对于新手和老手都有很大的帮助！希望大家看了以后能够大大的提高自己的水平！-FPGA in the embedded high-class courseware, the courseware is very useful for both novice and veteran of great help! I hope everyone saw the future can greatly improve the level of their own!
Platform: | Size: 11936768 | Author: 乔 | Hits:

[Other] zlg_avalon_lcd128_64

Description: 周立功 SOPC嵌入式系统实验教材 LCD12864驱动代码-SOPC Ligong week experimental materials embedded systems driven LCD12864 code
Platform: | Size: 19456 | Author: 周正波 | Hits:

[VHDL-FPGA-Verilog] BLDCM

Description: 基于Verilog HDL的直流无刷电机控制程序，Quartus II环境下编写。-Verilog HDL for BLDCM Control in Quartus II。
Platform: | Size: 198656 | Author: 琉璃 | Hits:

[VHDL-FPGA-Verilog] PWMproducer

Description: 这文件包是利用VHDL语言编写的产生PWM脉宽调制的程序，包含的文件都很全，大家可以下载学习一下。-this is a pwm program by vhdl,which conclude all fils.you can download this file and study.
Platform: | Size: 433152 | Author: 杨葱头 | Hits:

[VHDL-FPGA-Verilog] spi

Description: 基于CPLD的用SPI控制pwm的源码，用VHDL编写，已经测试，可以直接使用
Platform: | Size: 1024 | Author: DRzhou | Hits:

[VHDL-FPGA-Verilog] test1

Description: 利用pwm实现ad转换的VHDL语言源程序-Using PWM realization of VHDL language AD transform the source program
Platform: | Size: 693248 | Author: 王辉 | Hits:

[VHDL-FPGA-Verilog] FoxBone_PWM1

Description: This file is consist of VHDL regarding PWM Driver
Platform: | Size: 93184 | Author: changkyu | Hits:

[VHDL-FPGA-Verilog] DCmotor

Description: 给出了具体的基于FPGA的直流电机PWM控制VHDL程序，可用于毕业设计。-Given a specific FPGA-based DC motor PWM control VHDL program can be used to graduation.
Platform: | Size: 3188736 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] NCDividerAndItsApplicationVHDLSourceeCode

Description: 用VHDL编写的数控分频器及其仿真结果图片。该程序能实现PWM波形输出以及产生正负脉冲宽度可调的方波输出。-Prepared by the NC VHDL Simulation results divider and pictures. The program can achieve positive and negative PWM waveform output and pulse width adjustable square wave output.
Platform: | Size: 59392 | Author: 闫方义 | Hits:

[VHDL-FPGA-Verilog] pwmgen

Description: very, very simple pwm generator in vhdl
Platform: | Size: 1024 | Author: atm | Hits:

[SCM] mini-proj

Description: vhdl pulse with modulation(pwm) generetor
Platform: | Size: 114688 | Author: arrrfd | Hits:

[VHDL-FPGA-Verilog] Pwm_out

Description: 基于SOPC技术的pwm的VHDL语言设计-SOPC technology based on the VHDL language design pwm
Platform: | Size: 1024 | Author: hunaigang | Hits:

[VHDL-FPGA-Verilog] ep2c35_4_9_motor

Description: FPGA的电机控制程序，可对电机进行PWM的控制-it is writen by VHDL,the program generate PWMs to control the motor
Platform: | Size: 82944 | Author: Nevin Young | Hits:

[VHDL-FPGA-Verilog] VHDLPWM

Description: fpga输出pwm的vhdl程序，已经过开发板试验，绝对可用,包括所有文件。-fpga vhdl output pwm' s program has been developed plate test, absolutely free.
Platform: | Size: 451584 | Author: zhouhengjun | Hits:

[VHDL-FPGA-Verilog] Entrega-P2

Description: implementation PWM for Robot in VHDL
Platform: | Size: 217088 | Author: kalet_01 | Hits:

[VHDL-FPGA-Verilog] servomat

Description: antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "servo.vhd","servo" grados DSIN 50 pwm DSOUT 100 Create output port, assign port address <name> DSIO <port_id> Create readable output port, assign port address ORG 0 Programs always start at reset vector 0 EINT If using interrupts, be sure to enable the INTERRUPT input Inicio: <<< your code here >>> load talto,0 load tbajo,0 in cantidad_a,grados-antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "servo.vhd","servo" grados DSIN 50 pwm DSOUT 100 Create output port, assign port address <name> DSIO <port_id> Create readable output port, assign port address ORG 0 Programs always start at reset vector 0 EINT If using interrupts, be sure to enable the INTERRUPT input Inicio: <<< your code here >>> load talto,0 load tbajo,0 in cantidad_a,grados
Platform: | Size: 1057792 | Author: Jorge | Hits:

[VHDL-FPGA-Verilog] VHDL_PWM

Description: vhdl prog to design a PWM signal
Platform: | Size: 2048 | Author: skan | Hits:

[VHDL-FPGA-Verilog] 5589e6b62fd6

Description: doc vhdl to design a pwm signal to controling a C- C motor this doc is tested and was given good results-doc vhdl to design a pwm signal to controling a C- C motor this doc is tested and was given good results
Platform: | Size: 740352 | Author: skan | Hits:

[VHDL-FPGA-Verilog] report

Description: 利用VHDL语言实现基于pwm的D/A转换，要求，可以通过按键来分别选择占空比，从分别选择20,40,60,80。-Using VHDL language the pwm D/A conversion can be keys to select the duty cycle, from the Select 20, 40, 60, 80.
Platform: | Size: 76800 | Author: 琪 | Hits:

[VHDL-FPGA-Verilog] 2

Description: 利用VHDL语言编程，产生一组PWM波，PWM波的频率为10kHz,占空比00—100 可调-VHDL programming, resulting in a set of PWM wave PWM wave frequency is 10kHz, and 00-100 duty cycle adjustable
Platform: | Size: 1024 | Author: michael | Hits:
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